Conference

Embedded Systems Conference

New Sessions, New Tracks, New Opportunities.

If you can only attend one event this year, the ESC France is the must-attend event for embedded systems engineers. It is the place for the embedded community to meet, identify solutions to immediate design challenges and meet in person the solution providers for your next project.

ESC France brings together system architects, design engineers, suppliers, analysts and media from across the globe, including Asia and the Pacific Rim.

The following keynote talks are already planned:

• "The 21st Century Business Model Adventure" by Eric Schorn, Vice President of Marketing, Processor Division, ARM Ltd
• "Prototyping Using IP at Multiple Abstraction Levels Enables Embedded Software Development" by Joachim Kunkel, Vice President and General Manager, Solutions Group, Synopsys
• "Strategies for Managing SoC IP Risks at Advanced Process Nodes" by Yervant Zorian, Vice President & Chief Scientist, Virage Logic
• "Embedded Software - Technologies and Trends" by Bernard Candaele, Deputy Director Embedded Systems TBU, Thales
• "Building High-performance lower power media-intensive consumer products isn't easy!" by Michael Dimelow, Director of Marketing, Processor Division, ARM
• "Innovation by Cooperation in Embedded Signal Processing Systems" by Peter Simkens, Managing Director, DSP Valley

Panels:

• "IP Reuse vs. IP Leverage: What's the difference, and what are the issues?" moderated by Kathryn Kranen from Jasper Design Automation with the participation of Kathryn Kranen from Jasper Design Automation, Ron Collett from Numetrics, Olivier Haller from STMicroelectronics
• "Low volume designs that don't Always Stay That Way: Silicon industry solutions From Fabless chips to FPGAs" with the participation of Kalar Rajendiran from eSilicon, Hal Barbour from Cast, Gabriel Pulini from Abound Logic, Helena Krupnova from STMicro, Achronix, Altera
• "The evolution of semiconductor business models: is the fabless dead or alive and kicking?" organized by C. Paul Slaby from Kaben Wireless Silicon Inc with the participation of Stan Swirhun from Zarlink Semiconductor, Kalar Rajendiran from eSilicon
• "Improving IP Quality vs. Losing Design Productivity - What Are the Tradeoffs?" organized by Michel Tabusse from Satin IP with the participation of François Rémond from STMicroelectronics, Philippe Di Crescenzo from Arteris, Kathryn Kranen from Jasper Design Automation, Michel Tabusse from Satin IP Technologies
• "Design and Reuse -The impossible dream?" organized by Jack Browne from Sonics
• "Transactors: where the virtual world meets the implementation world" organized by Miguel Koch from Eve, moderated by Laurent Ducousso from ST with the participation of Heiko Mauersberger from Synopsys, Antoine Perrin from ST, Kenneth Larsen from Mentor, Luc Burgun from EVE, Xavier Buisson from CoWare
• "System Level IP: Challenges and Issues"organized by Bernard Candaele from Thales with the participation of Phil Dworsky from Synopsys, Bernard Candaele from Thales
• "Debug and optimisation of embedded software & SoC designs: can scalable on-chip system visibility be delivered cost-effectively?" organized by Serge Poublan from ARM, moderated by Michael Dimelow from ARM with the participation of Serge Poublan from ARM
• "From Processors to FPGAs to SoCs ? what are the best solutions to program algorithms onto hardware?" moderated by Jacques Benkoski from USVP (Executive Chairman, Synfora) with the participation of Jean-Louis Brelet from Xilinx, Christophe Bianchi from Synfora
• "Silicon IP, Verification IP, Software Drivers, and design kits for a total IP solution" organized by Jonah McLeod from Arasan Chip Systems with the participation of Ram Gopalan from Arasan Chip Systems, Paul Berkhuizen from ST Ericsson
• "R&D in Europe teams up to master future system design" with the participation of Michel Tabusse from Satin IP, Ivan Ring Nielsen, Infineon, ENIAC/CATRENE, Jurgen Haase from EDA Centrum

Visionary scientific seminars on key topics organized by gurus in the field, including invited state of the art academic presentations. Are already planned seminars on:

• Future in IP interconnects: optical, 3-D, wireless, what are the main challenges?
• Next massively Parallel computing with presentations from Peter Marwedel (Technische Universität Dortmund, Germany)
• TLM Verification for Systems-on-Chip with presentations from Bosch, Infineon, Siemens, FZI, Velten, Esen, Ecker (Infineon ), Stefan Lämmermann (University of Tübingen)
• Computational Models for Embedded Software with presentations from Fabrice Lemonnier (Thalès)
• IP Management for internal and External IPs with presentations from Philippe Ozil (Design And Reuse), Gabriele Saucier (Design And Reuse), Philippe Ozil (Design And Reuse)

Technical sessions discussing the issues to be solved in the IP-based system design arena.